The embodiments of the invention relate generally to the fabrication of semiconductor structures and more particularly to the fabrication of CMOS devices having two different semiconductor channel materials on a common semiconductor substrate with dual raised source and drains.
Leading edge Si CMOS industry is facing strong limitations with Si for 10 nm node sizes and beyond. One promising approach to achieving sub-10 nm geometry devices is co-integration of SixGe1-x (where x=0 to 1) p-FETs with group III-V compound n-FETs.
In devices with raised source and drains, the source and drain layers are formed above the channel material to achieve low series resistance.
N-FETs and p-FETs need a different selective epitaxy step to form the raised source and drain regions. These two epitaxy steps are typically done one after the other, wherein a first spacer layer is used to mask the p-regions while growing the n-regions and a second spacer layer is used to mask the n-regions while growing the p-regions. This leads to two different final spacer thicknesses for n-FETs and p-FETs.